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NCP1337 PWM Current-Mode Controller for Free Running Quasi-Resonant Operation
The NCP1337 combines a true current mode modulator and a demagnetization detector which ensures full Borderline/Critical Conduction Mode in any load/line conditions together with minimum drain voltage switching (Quasi-Resonant operation). The transformer core reset detection is done internally, without using any external signal, due to the Soxyless concept. The frequency is internally limited to 130 kHz, preventing the controller to operate above the 150 kHz CISPR-22 EMI starting limit. By monitoring the feedback pin activity, the controller enters ripple mode as soon as the power demand falls below a predetermined level. As each restart is softened by an internal soft-start, and as the frequency cannot go below 25 kHz, no audible noise can be heard. The NCP1337 also features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses and enters a safe burst mode, trying to restart. Once the default has gone, the device auto-recovers. Also included is a bulk voltage monitoring function (known as brown-out protection), an adjustable overpower compensation, and a VCC OVP. Finally, an internal 4.0 ms soft-start eliminates the traditional startup stress.
Features http://onsemi.com MARKING DIAGRAM
PDIP-7 P SUFFIX CASE 626B 1 8 SOIC-7 D SUFFIX CASE 751U P1337 AYWW G 1 NCP1337P AWL YYWWG
* * * * * * * * * * * * * * * * * * * *
Free-Running Borderline/Critical Mode Quasi-Resonant Operation Current-Mode Soft Ripple Mode with Minimum Switching Frequency for Standby Auto-Recovery Short-Circuit Protection Independent of Auxiliary Voltage Overvoltage Protection Brown-Out Protection Two Externally Triggerable Fault Comparators (one for a disable function, and the other for a permanent latch) Internal 4.0 ms Soft-Start 500 mA Peak Current Drive Sink Capability 130 kHz Max Frequency Internal Leading Edge Blanking Internal Temperature Shutdown Direct Optocoupler Connection Dynamic Self-Supply with Levels of 12 V (On) and 10 V (Off) SPICE Models Available for TRANsient and AC Analysis These are Pb-Free Devices* AC-DC Adapters for Notebooks, etc. Offline Battery Chargers Consumer Electronics (DVD Players, Set-Top Boxes, TVs, etc.) Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
A WL Y, YY WW G G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package = Pb-Free Package
PIN CONNECTIONS
BO FB CS GND 4 (Top View) 5 1 2 3 6 VCC DRV 8 HV
ORDERING INFORMATION
Device NCP1337PG NCP1337DR2G Package PDIP-7 (Pb-Free) SOIC-7 (Pb-Free) Shipping 50 Units/Tube 2500 Tape & Reel
Typical Applications
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
July, 2006 - Rev. 2
Publication Order Number: NCP1337/D
NCP1337
PIN FUNCTION DESCRIPTION
Pin No. 1 Symbol BO Function Brown-out and external triggering Description
* * *
By connecting this pin to the input voltage through a resistor divider, the controller ensures operation at a safe mains level. If an external event brings this pin above 3.0 V, the controller's output is disabled. If an external event brings this pin above 5.0 V, the controller is permanently latched-off. By connecting an optocoupler or an auxiliary winding to this pin, the peak current setpoint is adjusted accordingly to the output power demand. When the requested peak current setpoint is below the internal standby level, the device enters soft ripple mode. This pin senses the primary current and routes it to the internal comparator via an L.E.B. Inserting a resistor in series with the pin allows to control the overpower compensation level.
2
FB
Sets the peak current setpoint
* *
3
CS
Current sense input and overpower compensation adjustment
* * * * * *
4 5 6
GND DRV VCC
IC ground Output driver IC supply To be connected to an external MOSFET. Connected to a tank capacitor (and possibly an auxiliary winding). When VCC reaches 18.6 V, an internal OVP stops the output pulses. Connected to the high-voltage rail, this pin injects a constant current into the VCC bulk capacitor and ensures a clean lossless startup sequence.
8
HV
High-voltage pin
VOUT NCP1337 BO 1 + Cbulk 2 3 4 6 5 VCC Rcomp 8 + VCC +
Figure 1. Typical Application Schematic
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NCP1337
- + +
3V BO
+
5V
S R
Q
PERM. LATCH Vdd VCC < 4 V
TSD
8 ms timeout
35 ms max Toff Toff 5.5 ms blanking Ton VCC Q Q Toff R1 R2 Inhib
Soxyless demag detection
+ -
DISABLE Vdd 10 mA
TSD S
Startup
Soxyless Ton 7.5 ms min period SStart
Clk D
VBO
+
500 mV
+ -
BOK
DRV
OVP
100 mV Vdd 130 mV FB 3V 20 kHz Low-pass filter
+
- +
Skip SSkip
Ton
67 ms max Ton Soxyless
Setpoint
- +
TSD CS comp. PERM. LATCH SSkip
12 V 10 V 5V
HV
+
+ -
9.5 mA or 600 mA VCC
500 mV
Vdd
VBO
FAULT if Zener activated
300 ms Soft-Skipt
FAULT Management*
70 mA x VBO - 35 mA
4 ms soft-start
SStart
OVP
- + +
18.6 V
CS
Ton 4k 350 ns LEB 2p FAULT (*If FAULT duration > 80 ms = > STOP Restart when 2nd time VCC = VCCon)
GND
Figure 2. Internal Circuit Architecture
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NCP1337
MAXIMUM RATINGS
Rating Voltage on Pin 8 (HV) when Pin 6 (VCC) is Decoupled to Ground with 10 mF Maximum Current in Pin 8 (HV) Power Supply Voltage, Pin 6 (VCC) and Pin 5 (DRV) Maximum Current in Pin 6 (VCC) Maximum Voltage on all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) Maximum Current into all Pins except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (DRV) Maximum Current into Pin 6 (DRV) during ON Time and TBLANK Maximum Current into Pin 6 (DRV) after TBLANK during OFF Time Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Air, SOIC Version Thermal Resistance, Junction-to-Air, DIP Version Maximum Junction Temperature Operating Temperature Range Storage Temperature Range ESD Capability, HBM Model per Mil-std-883, Method 3015 (All Pins except HV) ESD Capability, Machine Model Symbol VHV - VCCmax - - - - - RqJC RqJA RqJA TJMAX - - - - Value -0.3 to 500 20 -0.3 to 20 "30 -0.3 to 10 "10 "1.0 "15 57 178 100 150 -40 to +125 -60 to +150 2.0 200 Unit V mA V mA V mA A mA C/W C/W C/W C C C kV V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78.
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NCP1337
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = 0C to +125C, Max TJ = 150C,
VCC = 11 V, unless otherwise noted.) Characteristic SUPPLY SECTION VCC Increasing Level at which the Controller Starts VCC Decreasing Level at which the Controller Stops Protection Mode is Activated if VCC reaches this Level whereas the HV Current Source is ON VCC Decreasing Level at which the Latch-Off Phase Ends Margin between VCC Level at which Latch Fault is Released and VCCLATCH VCC Increasing Level at which the Controller Enters Protection Mode VCC Level below which HV Current Source is Reduced Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz Internal IC Consumption, Latch-Off Phase, VCC = 8.0 V Internal IC Consumption in Skip INTERNAL STARTUP CURRENT SOURCE Minimum Guaranteed Startup Voltage on HV Pin High-Voltage Current Source when VCC > VCCINHIB (VCC = 10.5 V, VHV = 60 V) High-Voltage Current Source when VCC < VCCINHIB (VCC = 0 V, VHV = 60 V) Leakage Current Flowing when the HV Current Source is OFF (VCC = 17 V, VHV = 500 V) DRIVE OUTPUT Output Voltage Rise-Time @ CL = 1.0 nF, 10-90% of Output Signal Output Voltage Fall-Time @ CL = 1.0 nF, 10-90% of Output Signal Source Resistance Sink Resistance TEMPERATURE SHUTDOWN Temperature Shutdown Hysteresis on Temperature Shutdown CURRENT COMPARATOR Maximum Internal Current Setpoint (@ IFB = IFB100%) Minimum Internal Current Setpoint (@ IFB = IFBrippleIN) Internal Current Setpoint for IFB = IFBrippleOUT Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking Duration Internal Current Offset Injected on the CS Pin during ON Time (Over Power Compensation) @ 1.0 V on Pin 1 and Vpin3 = 0.5 V @ 2.0 V on Pin 1 and Vpin3 = 0.5 V Maximum ON Time 3 3 3 3 3 3 VCSLimit VCSrippleIN VCSrippleOUT TDEL TLEB IOPC - - 5 MaxTON 52 35 105 67 - - 82 ms 475 - - - - 500 100 130 120 350 525 - - 150 - mV mV mV ns ns mA - - TSD - 130 - - 30 - - C C 5 5 5 5 TR TF ROH ROL - - - - 50 20 20 8.0 - - - - ns ns W W 8 8 8 8 VHVmin IC1 IC2 IHVLeak - 5.5 0.3 - - 9.5 0.6 - 55 15 1.1 90 V mA mA mA 6 6 6 6 - 6 6 6 6 6 6 VCCON VCCMIN VCCOFF VCCLATCH VMARGIN VCCOVP VCCINHIB ICC1 ICC2 ICC3 ICCLOW 11 9.0 - 3.6 0.3 17.6 - - - - - 12 10 9.0 5.0 - 18.6 1.5 1.2 2.0 600 600 13 11 - 6.0 - 19.6 - - - - - V V V V V V V mA mA mA mA Pin Symbol Min Typ Max Unit
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NCP1337
ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25C, for min/max values TJ = 0C to +125C,
Max TJ = 150C, VCC = 11 V, unless otherwise noted.) Characteristic FEEDBACK SECTION FB Current under which FAULT is Detected FB Current for which Internal Setpoint is 100% FB Current above which DRV Pulses are Stopped FB Current under which DRV Pulses are Reauthorized after having reached IFBrippleIN FB Current above which FB Pin Voltage is not Regulated anymore FB Pin Voltage when IFBopen < IFB < IFBregMax Duration before Entering Protection Mode after FAULT Detection Internal Soft-Start Duration (Up to VCSLimit) Internal Soft-Skip Duration (Up to VCSLimit) BROWN-OUT AND LATCH SECTION Brown-Out Detection Level Current Flowing out of Pin 1 when Brown-Out Comparator has Toggled Vpin1 Threshold that Disables the Output Vpin1 Threshold that Activates the Permanent Latch DEMAGNETIZATION DETECTION BLOCK Current Threshold for Demagnetization Detection Max Voltage on DRV Pin During OFF Time after TBLANK (when Sinking 15 mA) Min Voltage on DRV Pin During OFF Time after TBLANK (when Sourcing 15 mA) Propagation Delay from Demag Detection to Gate ON State (IGATE Slope of 500 A/s) Blanking Window after Gate OFF State before Detecting Demagnetization Timeout on Demag Signal Maximum OFF Time Minimum Switching Period 5 5 5 5 5 5 5 5 ISOXYth VDRVlowMAX VDRVlowMIN TDMG TBLANK TOUT MaxTOFF MinPeriod - - -0.6 - - - - 6.8 210 - - 180 5.5 8.0 35 7.7 - 1.5 - 220 - - 42 8.5 mA V V ns ms ms ms ms 1 1 1 1 VBO IBO VDISABLE VLATCH 460 - 2.8 4.75 500 10 3.0 5.0 540 - 3.3 5.25 mV mA V V 2 2 2 2 2 2 - - - IFBopen IFB100% IFBrippleIN IFBrippleOUT IFBregMax VFB TFAULT TSS TSSkip - - - - - 2.8 - - - 40 50 220 205 500 3.0 80 4.0 300 - - - - - 3.2 - - - mA mA mA mA mA V ms ms ms Pin Symbol Min Typ Max Unit
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NCP1337
APPLICATION INFORMATION INTRODUCTION The NCP1337 implements a standard current mode architecture where the switch-off time is dictated by the peak current setpoint, whereas the core-reset detection triggers the turn-on event. This component represents the ideal candidate where low part-count is the key parameter, particularly in low-cost AC-DC adapters, consumer electronics, auxiliary supplies, etc. Due to its high-performance, high-voltage technology, the NCP1337 incorporates all the necessary features needed to build a rugged and reliable Switch-Mode Power Supply (SMPS): * Quasi-Resonant Operation: Valley-switching operation is ensured whatever the operating conditions are, due to the internal soxyless circuitry. As a result, there are virtually no primary switch turn-on losses, and no secondary diode recovery losses, and EMI and video noise perturbations are reduced. The converter also stays a first-order system and accordingly eases the feedback loop design. * Dynamic Self-Supply (DSS): Due to its Very High Voltage Integrated Circuit (VHVIC) technology, ON Semiconductor's NCP1337 allows for a direct pin connection to the high-voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent VCC level. As a result, low power applications will not require any auxiliary winding to supply the controller. In applications where this winding is anyway required (see "Power Dissipation" section in the application note), the DSS will simplify the VCC capacitor selection. * Overcurrent Protection (OCP): When the feedback current is below minimum value, a fault is detected. If this fault is present for more than 80 ms, NCP1337 enters an auto-recovery soft burst mode. All pulses are stopped and the VCC capacitor discharges down to 5.0 V. Then, by monitoring the VCC level, the startup current source is activated ON and OFF to create a burst mode. After the current source being activated twice, the controller tries to restart, with a 4.0 ms soft-start. If the fault has gone, the SMPS resumes operation. If the fault is still there, the burst sequence starts again. The soft-start, together with a minimum frequency clamp, allow to reduce the noise generated in the transformer in short-circuit conditions. Overvoltage Protection (OVP): By continuously monitoring the VCC voltage level, the NCP1337 stops switching whenever an overvoltage condition is detected. Brown-Out Detection (BO): By monitoring the level on Pin 1 during normal operation, the controller protects the SMPS against low mains condition. When Pin 1 level falls below 500 mV, the controller stops pulsing until this level goes back and resumes operation. By adjusting the resistor divider connected between the high input voltage and this pin, start and stop levels are programmable. Over Power Compensation (OPC): An internal current source injects out of Pin 3 (CS pin) a current proportional to the voltage applied on Pin 1. As this voltage is an image of the input voltage, by inserting a resistor in series with Pin 3, it is possible to create an offset on the current sense signal that will compensate the effect of the input voltage variation. External Latch Trip Point: By externally forcing a level on Pin 1 (e.g., with a signal coming from a temperature sensor) greater than 3.0 V (but below 5.0 V), it is possible to disable the output of the controller. If the voltage is forced over 5.0 V, the controller is permanently latched-off: to resume normal operation, the VCC voltage should go below 4.0 V, which implies to unplug the SMPS from the mains. Standby Ability: Under low load conditions, NCP1337 enters a Soft-Skip mode: when the CS setpoint becomes lower than 20% of the maximum peak current, output pulses are stopped, then switching is starting again when FB loop forces a setpoint higher than 25%. As this occurs at low peak current, with Soft-Skip activated, and as the TOFF is clamped, noise-free operation is guaranteed, even with a cheap transformer.
*
*
*
*
*
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NCP1337
Timing Diagrams
VCC VCCON VCCMIN At startup, a 4.0 ms soft-start is activated. If the current Setpoint is above the fault level, FAULT flag is raised.
CS Setpoint Fault
VCSstby
CS VCSLimit
FAULT
SS
TIMER 80 ms
When FAULT is activated, the 80 ms timer starts.
When the timer ends, if FAULT is not activated anymore, the controller works normally.
Figure 3. Startup Sequence
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NCP1337
VCC VCCON VCCMIN Restart on 2nd cycle
VCCLATCH
CS Setpoint Fault
Overload
Overload is removed here
When the current setpoint rises above fault level, FAULT flag is activated.
CS VCSLimit Output pulses are stopped.
FAULT SS
TIMER 80 ms
When FAULT flag is activated, timer is restarted.
80 ms Fault Timer
Normal Startup
Figure 4. Overload
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NCP1337
VCC
VCCon VCCmin
CS Setpoint
VCSrippleOUT VCSrippleIN
CS (envelope)
Min TON Soft-start on each re-start
Figure 5. Soft Ripple Mode in Standby
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NCP1337
Soxyless
The "Valley point detection" is based on the observation of the Power MOSFET Drain voltage variations. When the transformer is fully demagnetized, the Drain voltage evolution from the plateau level down to the VIN asymptote is governed by the resonating energy transfer between the LP transformer inductor and the global capacitance present on the Drain. These voltage oscillations create current oscillation in the parasitic capacitor across the switching
MOSFET (modelized by the Crss capacitance between Gate and Drain): a negative current (flowing out of DRV pin) takes place during the decreasing part of the Drain oscillation, and a positive current (entering into the DRV pin) during the increasing part. The Drain valley corresponds to the inversion of the current (i.e., the zero crossing): by detecting this point, we always ensure a true valley turn-on.
Lprim Isoxy Crss
Vswitch
TSWING
DRV
t
Figure 6. Soxyless Concept
The current in the Power MOSFET gate is: Igate = Vringing/Zc (with Zc the capacitance impedance) so Igate = Vringing S (2 S p S Fres S Crss) The magnitude of this gate current depends on the MOSFET, the resonating frequency and the voltage swing present on the Drain at the end of the plateau voltage. The dead time TSWING is given by the equation:
Tswing + 0.5 Fres + p * Lp * Cdrain
(eq. 1)
Drain. This capacitance includes the snubber capacitor if any, the transformer windings stray capacitance plus the parasitic MOSFET capacitances COSS and CRSS).
Internal Feedback Circuitry
(where LP is the primary transformer inductance and CDRAIN the total capacitance present on the MOSFET
To simplify the implementation of a primary regulation, it is necessary to inject a current into the FB pin (instead of sourcing it out). But to have a precise primary regulation, the voltage present on FB pin must be regulated. Figure 8 gives the FB pin internal implementation: the circuitry combines the functions of a current to voltage converter and a voltage regulator.
Vdd FB + + - Internal Setpoint
3V
20 kHz Low-pass Filter
Figure 7. Internal Implementation of FB Pin
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NCP1337
The input information is the current injected in FB pin by the feedback loop. The range of current is from 40 mA for overload detection to 220 mA corresponding to VCSrippleIN. In transients, currents from 0 to more than 400 mA may also appear: the circuitry is able to sustain them. To regulate the FB pin voltage, the operational amplifier needs to have a high gain and a wide bandwidth. But the feedback information used internally needs to be filtered, because we don't want the controller to be sensitive to the switching noise. For this purpose, a 20 kHz filter is added after the shunt regulator, and any reading of the feedback signal (for ripple mode, fault detection, or setpoint elaboration) is done after.
Soft Burst Mode (Protection Mode)
current source is turned on each time VCC reaches VCCLATCH, maintaining VCC between 5.0 V and 12 V): the controller stays in this position until the VCC voltage is decreased below 4.0 V, i.e., when the power supply is unplugged from the mains (in normal operation, as soon as a voltage is present on the HV pin, VCC is always kept above 5.0 V).
Soft Ripple Mode
The NCP1337 features a fault timer to detect an overload completely independently of the VCC voltage. As soon as the feedback loop asks for the maximum power, a fault is detected, and an internal timer is started. When the fault disappears the timer is reset, but if the timer reaches 80 ms, the protection mode is activated. Once this protection is toggled, output pulses are stopped and DSS is deactivated (HV current source turn-on threshold changes from VCCMIN to VCCLATCH). VCC slowly decreases (the current consumption is ICC3), and the HV current source is switched ON when VCC reaches VCCLATCH. As a result VCC increases until VCCON, but the controller does not start as the output is still forced low. VCC decreases again down to VCCLATCH, and a new start-up cycle occurs. On the second attempt, the output is released, and NCP1337 effectively starts, with the soft-start activated. Figure 4 illustrates this behavior.
Safety Features
The soft ripple mode is a skip mode with a large hysteresis on the skip comparator in order to ensure a noise-free and high-efficiency operation in low-load conditions (standby). When internal setpoint is reaching VCSrippleIN = 100 mV (corresponding to 20% of the maximum setpoint), the output pulses are stopped. Then FB loop asks for more power and internal setpoint is increasing: when it reaches VCSrippleOUT = 130 mV (corresponding to 25% of the maximum setpoint), the output starts pulsing again. Soft-start is activated in each activity following a stop period. See Figure 5 for detailed timing diagram.
HV Current Source
The NCP1337 includes several safety features to help the power supply designer to build a rugged design: * OVP (Overvoltage on VCC): Activated when voltage on pin VCC is higher than 18.6 V * Brown-Out (Undervoltage lockout on bulk voltage): Activated when voltage on pin BO is below 500 mV * Disable (Comparator activated by an external signal): Activated when the voltage on BO pin is higher than 3.0 V but below 5.0 V * TSD (Temperature shutdown): Typically activated when the die temperature is above 150C, released at 120C All these events have the same consequence for the controller: the DRV pulses are stopped. When the condition disappears, the controller restarts with the soft-start activated. * Permanent Latch (Comparator activated by an external signal): Activated when the voltage on BO pin is above 5.0 V When this comparator is activated, the DRV pulses are stopped, and the DSS is deactivated (only the start-up
NCP1337 features a DSS, to allow operation without any auxiliary voltage. But to protect the die in case of short-circuit on VCC pin, the current delivered by the HV current source is lowered when VCC voltage is below 1.5 V. In the case the current consumed on the DRV pin is higher than the DSS capability (high Qg MOSFET or failure), the HV current source is switched ON when VCC reaches VCCMIN, but the voltage on VCC pin keep on decreasing. If there is no UVLO threshold to stop the DRV pulses, the gate voltage will become too low and the risk is high to destroy the MOSFET. NCP1337 features an additional comparator, which threshold is 9.0 V: when VCC reaches this level whereas the HV current source is ON, DRV pulses are stopped and the protection mode is activated.
Brown-Out
The brown-out protection comparator has a fixed reference of 500 mV. When the comparator is activated (i.e., when the input voltage VIN is above the starting level), a 10 mA internal current source is activated and creates an offset across the bottom resistor of the external resistor divider. It gives the minimum hysteresis of the brown-out protection. By adding a series resistor between the divider and the BO pin, it is possible to adjust (increase) the hysteresis. The BO pin also features two additional comparators: the first one (that toggles at 3.0 V) stops the DRV pulses, whereas the second one (that toggles at 5.0 V) permanently latches off the controller (the VCC should be forced below 4.0 V to release the latch). Figure 8 gives the internal implementation of the BO pin.
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NCP1337
+ + - Permanent Latch
5V
+ + - Enable
3V
Vin 3.3 meg Rhyst BO
Vdd 10 mA current source activated when VBOK is high + + 11 k 500 mV - BOK
Figure 8. Internal Implementation of BO Pin
PACKAGE DIMENSIONS
SOIC-7 D SUFFIX CASE 751U-01 ISSUE C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
-A-
8 5
-B- S
1 4
0.25 (0.010)
M
B
M
G C -T- H D 7 PL 0.25 (0.010)
M SEATING PLANE
R
X 45 _
J M TB
S
K
DIM A B C D G H J K M N S
A
S
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NCP1337
PACKAGE DIMENSIONS
PDIP-7 P SUFFIX CASE 626B-01 ISSUE A
J
8 5
M B L
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 5. DIMENSIONS A AND B ARE DATUMS. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10 0.76 1.01
1
4
F
NOTE 2
A
C -T-
SEATING PLANE
N D G K B
M
H 0.13 (0.005)
M
TA
M
Soft-Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). The product described herein (NCP1337), may be covered by the following U.S. patents: 6,362,067, 5,073,850, 6,385,060, 6,587,357, 6,469,484, 6,940,320, 5,862,045. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP1337/D

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